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| MC74LVX259 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL-Compatible Inputs The MC74LVX259 is an 8-bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The LVX259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table.. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the LVX259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MC74LVX259 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74LVX259 to be used to interface 5 V circuits to 3 V circuits. http://onsemi.com MARKING DIAGRAMS 16 9 LVX259 AWLYYWW SOIC-16 D SUFFIX CASE 751B 1 8 16 9 TSSOP-16 DT SUFFIX CASE 948F 1 LVX 259 AWLYWW 8 9 16 SOIC EIAJ-16 M SUFFIX CASE 966 LVX259 ALYW 1 8 * * * * * * * * * High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC CMOS-Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device MC74LVX259D MC74LVX259DR2 MC74LVX259DT MC74LVX259DTR2 MC74LVX259M MC74LVX259MEL Package SO-16 SO-16 TSSOP-16 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail TSSOP-16 2000 Units/Reel SO EIAJ-16 48 Units/Rail SO EIAJ-16 2000 Units/Reel (c) Semiconductor Components Industries, LLC, 2001 1 April, 2001 - Rev. 1 Publication Order Number: MC74LVX259/D MC74LVX259 A0 A1 A2 Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A0 RESET ENABLE A2 DATA IN Q7 Q6 Q5 Q4 RESET ENABLE 15 14 DATA IN 13 ADDRESS INPUTS A1 4 1 2 3 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS PIN 16 = VCC PIN 8 = GND Figure 1. Pin Assignment Figure 2. Logic Diagram A0 A1 A2 1 2 3 BIN/OCT 1 2 4 0 1 2 3 4 4 5 6 7 8 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 A0 A1 A2 1 2 3 DMUX 0 0 G 7 2 0 1 2 3 4 4 5 6 7 8 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 13 14 15 ID EN R 5 6 7 13 14 15 ID EN R 5 6 7 Figure 3. IEC Logic Symbol MODE SELECTION TABLE Enable L H L H LATCH SELECTION TABLE Address Inputs C L L L L H H H H B L L H H L L H H A L H L H L H L H Reset H H L L Mode Addressable Latch Memory 8-Line Demultiplexer Reset Latch Addressed Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 http://onsemi.com 2 MC74LVX259 DATA INPUT 13 D 4 Q0 D 5 Q1 D 6 Q2 D A0 7 Q3 ADDRESS INPUTS A1 3 TO 8 DECODER D 9 Q4 A2 D ENABLE 14 10 Q5 D 11 Q6 D 12 Q7 RESET 15 Figure 4. Expanded Logic Diagram http://onsemi.com 3 MC74LVX259 MAXIMUM RATINGS (Note 1.) Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 2.) Machine Model (Note 3.) Charged Device Model (Note 4.) Above VCC and Below GND at 125C (Note 5.) SOIC Package TSSOP SOIC Package TSSOP Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V ILATCH-UP qJA Latch-Up Performance mA C/W Thermal Resistance, Junction to Ambient 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22-A114-A 3. Tested to EIA/JESD22-A115-A 4. Tested to JESD22-C101-A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V Characteristics Min 2.0 0 0 -40 0 Max 3.6 5.5 VCC 85 100 Unit V V V C ns/V http://onsemi.com 4 MC74LVX259 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage High-Level Output g V lt Voltage IOH = -50 A IOH = -50 A IOH = -4 mA VOL Low-Level Output Voltage V lt IOL = 50 A IOL = 50 A IOL = 4 mA IIN ICC Input Leakage Current Maximum Quiescent Supply Current (per package) VIN = 5.5 V or GND VIN = VCC or GND Condition (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 0 to 3.6 3.6 1.0 1.0 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 0.1 2.0 2.0 3.0 Min 0.75 VCC 0.7 VCC 0.7 VCC 0.25 VCC 0.3 VCC 0.3 VCC 1.9 2.9 2.48 0.1 0.1 0.44 1.0 A A V TA = 25C Typ Max -40C TA 85C Min 0.75 VCC 0.7 VCC 0.7 VCC 0.25 VCC 0.3 VCC 0.3 VCC Max Unit V VIL V VOH V II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I I I II I I I I I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I III II III II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II III II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I III II I I I I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II III II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA = 25C Typ 6.3 9.0 5.6 8.0 6.3 9.0 5.6 8.0 6.3 9.0 5.6 8.0 6.3 9.0 5.6 8.0 6 -40C TA 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Symbol tPLH, tPHL Parameter Test Conditions Min Max Unit ns Maximum Propagation Delay, Data to Output (Figures 5 and 9) VCC = 2.7 V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 9.0 14.0 8.0 12.0 9.0 14.0 8.0 12.0 9.0 14.0 9.0 12.0 9.0 14.0 9.0 12.0 10 12.0 15.0 VCC = 3.3 V 0.3 V VCC = 2.7 V 11.0 14.0 tPLH, tPHL Maximum Propagation Delay, Address Select to Output (Figures 6 and 9) 12.0 15.0 ns VCC = 3.3 V 0.3 V VCC = 2.7 V 11.0 14.0 tPLH, tPHL Maximum Propagation Delay, Enable to Output (Figures NO TAG and 9) 12.0 15.0 ns VCC = 3.3 V 0.3 V VCC = 2.7 V 11.0 14.0 tPHL Maximum Propogation Delay, Reset to Output (Figures 7 and 9) 12.0 15.0 ns VCC = 3.3 V 0.3 V 11.0 14.0 10 CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 3.3 V 30 CPD Power Dissipation Capacitance (Note 6.) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 5 MC74LVX259 TIMING REQUIREMENTS Input tr = tf = 3.0 ns II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIII I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII I I I I TA = 25C Typ TA = 85CIII Max Unit Symbol Parameter Test Conditions VCC = 2.7 V Min 4.5 4.5 4.0 3.0 2.0 2.0 Max Min tw Minimum Pulse Width, Reset or Enable (Figure 8) 5.0III ns 5.0 4.0 3.0 2.0 2.0 VCC = 3.3 V 0.3 V VCC = 2.7 V tsu Minimum Setup Time, Address or Data to Enable (Figure 8) ns VCC = 3.3 V 0.3 V VCC = 2.7 V th Minimum Hold Time, Enable to Address or Data (Figure 7 or 8) Maximum Input, Rise and Fall Times (Figure 5) ns VCC = 3.3 V 0.3 V VCC = 2.7 V tr, tf 400 300 300 300 ns VCC = 3.3 V 0.3 V VCC tr 50% DATA IN GND tPLH 50% OUTPUT Q OUTPUT Q tPHL 50% tPHL 50% tPHL tf DATA IN GND VCC GND VCC GND VCC ADDRESS SELECT 50% Figure 5. Switching Waveform VCC DATA IN tw ENABLE 50% tPHL OUTPUT Q 50% 50% tPHL GN D tw GND VCC Figure 6. Switching Waveform VCC DATA IN tw RESET 50% GND tPHL OUTPUT Q 50% GND VCC Figure 7. Switching Waveform Figure 8. Switching Waveform TEST POINT DATA IN OR ADDRESS SELECT VCC 50% th(H) tsu ENABLE 50% GND *Includes all probe and jig capacitance tsu th(H) GND VCC DEVICE UNDER TEST OUTPUT CL * Figure 9. Switching Waveform http://onsemi.com 6 Figure 10. Test Circuit MC74LVX259 K t D TOP COVER TAPE P2 P0 10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2 mm (0.008") E A0 SEE NOTE 7. B1 K0 SEE NOTE 7. FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0 F W + B0 P + + D1 FOR COMPONENTS 2.0 mm x 1.2 mm AND LARGER EMBOSSMENT USER DIRECTION OF FEED CENTER LINES OF CAVITY *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE BENDING RADIUS EMBOSSED CARRIER EMBOSSMENT 10 MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE 100 mm (3.937") 1 mm MAX TAPE 1 mm (0.039") MAX TYPICAL COMPONENT CENTER LINE 250 mm (9.843") CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity Figure 11. Carrier Tape Specifications http://onsemi.com 7 MC74LVX259 EMBOSSED CARRIER DIMENSIONS (See Notes 8. and 9.) Tape Size 8 mm B1 Max 4.35 mm (0.179") D 1.5 mm + 0.1 -0.0 (0.059" ( 0 004 +0.004 -0.0) D1 1.0 mm Min (0.179") 1.5 mm Min (0.060) E 1.75 mm 0.1 (0.069 0.004") ) F 3.5 mm 0.5 (1.38 0.002") 5.5 mm 0.5 (0.217 0.002") K 2.4 mm Max (0.094") 6.4 mm Max (0.252") P 4.0 mm 0.10 (0.157 0.004") 4.0 mm 0.10 (0.157 0.004") 8.0 mm 0.10 (0.315 0.004") 4.0 mm 0.10 (0.157 0.004") 8.0 mm 0.10 (0.315 0.004") 12.0 mm 0.10 (0.472 0.004") 16.0 mm 0.10 (0.63 0.004") P0 4.0 mm 0.1 (0.157 0.004") ) P2 2.0 mm 0.1 (0.079 0.004") ) R 25 mm (0.98") T 0.6 mm (0.024) W 8.3 mm (0.327) 12 mm 8.2 mm (0.323") 30 mm (1.18") 12.0 mm 0.3 (0.470 0.012") 16 mm 12.1 mm (0.476") 7.5 mm 0.10 (0.295 0.004") 7.9 mm Max (0.311") 16.3 mm (0.642) 24 mm 20.1 mm (0.791") 11.5 mm 0.10 (0.453 0.004") 11.9 mm Max (0.468") 24.3 mm (0.957) 8. Metric Dimensions Govern-English are in parentheses for reference only. 9. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity http://onsemi.com 8 MC74LVX259 t MAX 1.5 mm MIN (0.06") 20.2 mm MIN (0.795") 13.0 mm 0.2 mm (0.512" 0.008") A 50 mm MIN (1.969") FULL RADIUS G Figure 12. Reel Dimensions REEL DIMENSIONS Tape Size 8 mm 8 mm 12 mm 16 mm 24 mm T&R Suffix T1, T2 T3, T4 R2 R2 R2 A Max 178 mm (7") 330 mm (13") 330 mm (13") 360 mm (14.173") 360 mm (14.173") G 8.4 mm, +1.5 mm, -0.0 (0.33" + 0.059", -0.00) 8.4 mm, +1.5 mm, -0.0 (0.33" + 0.059", -0.00) 12.4 mm, +2.0 mm, -0.0 (0.49" + 0.079", -0.00) 16.4 mm, +2.0 mm, -0.0 (0.646" + 0.078", -0.00) 24.4 mm, +2.0 mm, -0.0 (0.961" + 0.078", -0.00) t Max 14.4 mm (0.56") 14.4 mm (0.56") 18.4 mm (0.72") 22.4 mm (0.882") 30.4 mm (1.197") DIRECTION OF FEED BARCODE LABEL POCKET HOLE Figure 13. Reel Winding Direction http://onsemi.com 9 MC74LVX259 CAVITY TAPE TOP TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN COMPONENTS TAPE LEADER NO COMPONENTS 400 mm MIN DIRECTION OF FEED Figure 14. Tape Ends for Finished Goods User Direction of Feed Figure 15. TSSOP and SOIC R2 Reel Configuration/Orientation TAPE UTILIZATION BY PACKAGE Tape Size 8 mm 12 mm 16 mm 24 mm 8-Lead 14-, 16-Lead 18-, 20-, 24-, 28-Lead 8-, 14-, 16-Lead 20-, 24-Lead 48-, 56-Lead 8-, 14-, 16-Lead 20-, 24-Lead 48-, 56-Lead SOIC TSSOP QFN SC88A / SOT-353 SC88/SOT-363 5-, 6-Lead http://onsemi.com 10 MC74LVX259 PACKAGE DIMENSIONS SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.15 (0.006) T U S 0.25 (0.010) M A -V- N F DETAIL E C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E http://onsemi.com 11 CCC EE CCC EE -W- |
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